SPRS439M – JUNE 2007 – REVISED AUGUST 2012
is a block diagram of the SPI in slave mode.
SPIFFENA
SPIFFTX.14
RX FIFO registers
Receiver
Overrun Flag
SPISTS.7
Overrun
INT ENA
SPIRXBUF
RX FIFO _0
RX FIFO _1
SPICTL.4
−−−−−
RX FIFO _15
16
SPIRXBUF
Buffer Register
RX FIFO Interrupt
SPIINT/SPIRXINT
RX Interrupt
Logic
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
−−−−−
TX FIFO _1
TX FIFO _0
TX FIFO Interrupt
TX Interrupt
Logic
SPITXINT
SPI INT FLAG
SPISTS.6
SPICTL.0
SPI INT
ENA
16
SPITXBUF
Buffer Register
16
M
SPIDAT
Data Register
SPIDAT.15 − 0
S
M
S
Talk
SPICTL.1
16
M
S
SW1
M
S
SW2
SPISOMI
(A)
SPISIMO
SPISTE
State Control
Master/Slave
SPI Char
SPICCR.3 − 0
3
2
1
0
M
S
M
S
SW3
Clock
Polarity
SPICCR.6
1
0
Clock
Phase
SPICTL.3
SPICTL.2
SPI Bit Rate
LSPCLK
6
5
SPIBRR.6 − 0
4
3
2
SPICLK
A.
SPISTE is driven low by the master for a slave device.
Figure 4-16. SPI Module Block Diagram (Slave Mode)
Copyright © 2007–2012, Texas Instruments Incorporated
Peripherals
97
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