SPRS439M – JUNE 2007 – REVISED AUGUST 2012
3.6
System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes.
shows the various clock and reset domains that will be discussed.
C28x Core
SYSCLKOUT
Clock Enables
System
Control
Register
LOSPCP
Peripheral
Registers
Bridge
CLKIN
LSPCLK
I/O
SPI-A, SCI-A/B/C
Clock Enables
I2C-A
Clock Enables
Peripheral Bus
/2
I/O
GPIO
Mux
eCAN-A/B
Clock Enables
Bridge
Peripheral
Registers
I/O
ePWM1/../6, HRPWM1/../6, Peripheral
Registers
eCAP1/../6, eQEP1/2
Clock Enables
LSPCLK
LOSPCP
Peripheral
Registers
HISPCP
Bridge
I/O
McBSP-A/B
Clock Enables
HSPCLK
16 Channels
12-Bit ADC
Bridge
ADC
Registers
Result
Registers
Clock Enables
A.
CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT). See
for an illustration of how CLKIN is derived.
Figure 3-8. Clock and Reset Domains
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to the PCLKCR0, PCLKCR1, and
PCLKCR2 registers (enables peripheral clocks) occurs to when the action is valid. This delay
must be taken into account before attempting to access the peripheral configuration
registers.
Copyright © 2007–2012, Texas Instruments Incorporated
DMA
Bus
DMA
Memory Bus
Functional Overview
57
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