SPRS439M – JUNE 2007 – REVISED AUGUST 2012
6.15
6.16
6.17
6.18
6.14.7 External Interface Ready-on-Read Timing With One External Wait State
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6.14.8 External Interface Ready-on-Write Timing With One External Wait State
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6.14.9 XHOLD and XHOLDA Timing
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On-Chip Analog-to-Digital Converter
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6.15.1 ADC Power-Up Control Bit Timing
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6.15.2 Definitions
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6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
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6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
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6.15.5 Detailed Descriptions
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Multichannel Buffered Serial Port (McBSP) Timing
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6.16.1 McBSP Transmit and Receive Timing
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6.16.2 McBSP as SPI Master or Slave Timing
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Flash Timing
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Migrating Between F2833x Devices and F2823x Devices
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7
8
9
L-to-M Revision History
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K-to-L Revision History
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Thermal and Mechanical Data
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4
Contents
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