SPRS439M – JUNE 2007 – REVISED AUGUST 2012
6.15.1 ADC Power-Up Control Bit Timing
ADC Power Up Delay
PWDNBG
ADC Ready for Conversions
PWDNREF
t
d(BGR)
PWDNADC
Request for
ADC
Conversion
t
d(PWD)
Figure 6-31. ADC Power-Up Control Bit Timing
Table 6-51. ADC Power-Up Delays
PARAMETER
(1)
t
d(BGR)
t
d(PWD)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
Delay time for power-down control to be stable. Bit delay time for band-gap
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
register (PWDNADC) must be set to 1 before any ADC conversions are initiated.
20
50
1
MIN
TYP
MAX
5
UNIT
ms
μs
ms
(1)
Timings maintain compatibility to the 281x ADC module. The 2833x/2823x ADC also supports driving all 3 bits at the same time and
waiting t
d(BGR)
ms before first conversion.
Table 6-52. Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
(1)
ADC OPERATING MODE
Mode A (Operational Mode):
Mode B:
•
•
•
•
•
•
•
•
•
•
•
CONDITIONS
BG and REF enabled
PWD disabled
ADC clock enabled
BG and REF enabled
PWD enabled
ADC clock enabled
BG and REF disabled
PWD enabled
ADC clock disabled
BG and REF disabled
PWD enabled
V
DDA18
30
9
V
DDA3.3
2
0.5
(2)
UNIT
mA
mA
Mode C:
5
20
μA
Mode D:
5
15
μA
(1)
(2)
Test Conditions:
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
V
DDA18
includes current into V
DD1A18
and V
DD2A18
. V
DDA3.3
includes current into V
DDA2
and V
DDAIO
.
170
Electrical Specifications
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