TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
Digital Signal Controllers (DSCs)
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SPRS439C–JUNE 2007–REVISED FEBRUARY 2008
4.13 GPIO MUX
On the F2833x/F2823x devices, the GPIO MUX can multiplex up to three independent peripheral signals
on a single GPIO pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block
diagram per pin is shown in Figure 4-18. Because of the open drain capabilities of the I2C pins, the GPIO
MUX block diagram for these pins differ. See the TMS320F2833x Digital Signal Controller (DSC) System
Control and Interrupts Reference Guide (literature number SPRUFB0) for details.
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLMPSEL
GPIOXINT7SEL
LPMCR0
GPIOXNMISEL
External Interrupt
MUX
Low Power
Modes Block
PIE
Asynchronous
path
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
N/C
00
01
Peripheral 1 Input
Peripheral 2 Input
Input
Internal
Pullup
Qualification
10
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
01
GPxDAT (latch)
Peripheral 1 Output
10
11
Peripheral 2 Output
Peripheral 3 Output
High Impedance
Output Control
GPxDIR (latch)
00
01
Peripheral 1 Output Enable
Peripheral 2 Output Enable
0 = Input, 1 = Output
XRS
10
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the
TMS320x2833x System Control and Interrupts Reference Guide (literature number SPRUFB0) for pin-specific
variations.
Figure 4-18. GPIO MUX Block Diagram
96
Peripherals
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