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TMS320F2812ZHHAR 参数 Datasheet PDF下载

TMS320F2812ZHHAR图片预览
型号: TMS320F2812ZHHAR
PDF下载: 下载PDF文件 查看货源
内容描述: [C2000™ 32-bit MCU with 150 MHz, 256 KB Flash, EMIF 179-BGA MICROSTAR -40 to 85]
分类和应用: 微控制器和处理器外围集成电路数字信号处理器装置可编程只读存储器时钟
文件页数/大小: 170 页 / 1662 K
品牌: TI [ TEXAS INSTRUMENTS ]
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www.ti.com
SPRS174S – APRIL 2001 – REVISED MARCH 2011
3.3
Register Map
The F281x and C281x devices contain three peripheral register spaces. The spaces are categorized as
follows:
Peripheral Frame 0:
Peripheral Frame 1:
Peripheral Frame 2:
These are peripherals that are mapped directly to the CPU memory bus.
See
These are peripherals that are mapped to the 32-bit peripheral bus.
See
These are peripherals that are mapped to the 16-bit peripheral bus.
See
Table 3-6. Peripheral Frame 0 Registers
(1)
NAME
ADDRESS RANGE
0x00 0880 – 0x00 09FF
0x00 0A00 – 0x00 0A7F
0x00 0A80 – 0x00 0ADF
0x00 0AE0 – 0x00 0AEF
0x00 0AF0 – 0x00 0B1F
0x00 0B20 – 0x00 0B3F
0x00 0B40 – 0x00 0BFF
0x00 0C00 – 0x00 0C3F
0x00 0C40 – 0x00 0CDF
0x00 0CE0 – 0x00 0CFF
0x00 0D00 – 0x00 0DFF
0x00 0E00 – 0x00 0FFF
SIZE (x16)
384
128
96
16
48
32
192
64
160
32
256
512
Not EALLOW protected
EALLOW protected
Not EALLOW protected
Not EALLOW protected
EALLOW protected
CSM Protected
EALLOW protected
ACCESS TYPE
(2)
EALLOW protected
Device Emulation Registers
Reserved
FLASH Registers
(3)
Code Security Module Registers
Reserved
XINTF Registers
Reserved
CPU-TIMER0/1/2 Registers
Reserved
PIE Registers
PIE Vector Table
Reserved
(1)
(2)
(3)
Registers in Frame 0 support 16-bit and 32-bit accesses.
If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS
instruction disables writes. This prevents stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-7. Peripheral Frame 1 Registers
(1)
NAME
eCAN Registers
eCAN Mailbox RAM
Reserved
(1)
ADDRESS RANGE
0x00 6000 – 0x00 60FF
0x00 6100 – 0x00 61FF
0x00 6200 – 0x00 6FFF
SIZE (x16)
256
(128 x 32)
256
(128 x 32)
3584
ACCESS TYPE
Some eCAN control registers (and selected bits in
other eCAN control registers) are EALLOW-protected.
Not EALLOW-protected
The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
Copyright © 2001–2011, Texas Instruments Incorporated
Functional Overview
39
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