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SPRS174S – APRIL 2001 – REVISED MARCH 2011
Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
(1)
NO.
M58
M59
M60
M61
(1)
t
su(DRV-CKXL)
t
h(CKXL-DRV)
t
su(FXL-CKXL)
t
c(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
2P
MASTER
MIN
30
1
MAX
SLAVE
MIN
8P – 10
8P – 10
16P + 10
16P
MAX
UNIT
ns
ns
ns
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
(1)
NO.
M53
M54
M56
M57
(1)
t
h(CKXH-FXL)
t
d(FXL-CKXL)
t
dis(CKXH-DXHZ)
t
d(FXL-DXV)
PARAMETER
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Disable time, DX high impedance following last data bit
from CLKX high
Delay time, FSX low to DX valid
MASTER
MIN
P
2P
P+6
6
7P + 6
4P + 6
MAX
SLAVE
MIN
MAX
UNIT
ns
ns
ns
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
LSB
CLKX
M53
FSX
M56
DX
Bit 0
M58
DR
Bit 0
Bit(n-1)
M57
Bit(n-1)
M55
(n-2)
M59
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
M54
M60
MSB
M61
Figure 6-48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
155
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