SPRS174S – APRIL 2001 – REVISED MARCH 2011
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Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
(1)
NO.
M49
M50
M51
M52
(1)
t
su(DRV-CKXH)
t
h(CKXH-DRV)
t
su(FXL-CKXL)
t
c(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
2P
MASTER
MIN
30
1
MAX
SLAVE
MIN
8P – 10
8P – 10
8P + 10
16P
MAX
UNIT
ns
ns
ns
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
(1)
NO.
M43
M44
M47
M48
(1)
t
h(CKXH-FXL)
t
d(FXL-CKXL)
t
dis(FXH-DXHZ)
t
d(FXL-DXV)
PARAMETER
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Disable time, DX high impedance following last data bit
from FSX high
Delay time, FSX low to DX valid
MASTER
MIN
2P
P
6
6
6P + 6
4P + 6
MAX
SLAVE
MIN
MAX
UNIT
ns
ns
ns
ns
2P = 1/CLKG.
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1.
With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.6875 MHz and P = 13.3 ns.
LSB
M51
MSB
M52
CLKX
M43
FSX
M47
DX
M48
M44
Bit 0
M49
Bit(n-1)
(n-2)
M50
(n-3)
(n-4)
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 6-47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
154
Electrical Specifications
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