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SPRS174S – APRIL 2001 – REVISED MARCH 2011
6.26 External Interface Ready-on-Read Timing With One External Wait State
Table 6-35. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
d(XCOHL-XRDL)
t
d(XCOHL-XRDH)
t
h(XA)XZCSH
t
h(XA)XRD
(1)
Delay time, XCLKOUT high to zone chip-select active-low
Delay time, XCLKOUT high/low to zone chip-select inactive-high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active-low
Delay time, XCLKOUT high/low to XRD inactive-high
Hold time, address valid after zone chip-select inactive-high
Hold time, address valid after XRD inactive-high
–2
(1)
(1)
MIN
–2
MAX
1
3
2
1
1
UNIT
ns
ns
ns
ns
ns
ns
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6-36. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
t
a(A)
t
a(XRD)
t
su(XD)XRD
t
h(XD)XRD
(1)
Access time, read data from address valid
Access time, read data valid from XRD active-low
Setup time, read data valid before XRD strobe inactive-high
Hold time, read data valid after XRD inactive-high
12
0
MAX
(LR + AR) – 14
(1)
AR – 12
(1)
UNIT
ns
ns
ns
ns
LR = Lead period, read access. AR = Active period, read access. See
Table 6-37. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
(1)
MIN
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
e(XRDYsynchH)
t
su(XRDYsynchH)XCOHL
t
h(XRDYsynchH)XZCSH
(1)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip-select high
15
0
15
12
3
MAX
UNIT
ns
ns
ns
ns
ns
The first XREADY (synchronous) sample occurs with respect to E in
E = (XRDLEAD + XRDACTIVE) t
c(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to
be low, it will be sampled again each t
c(XTIM)
until it is found to be high.
For each sample (n), the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) t
c(XTIM)
– t
su(XRDYsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
Table 6-38. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
(1)
MIN
t
su(XRDYAsynchL)XCOHL
t
h(XRDYAsynchL)
t
e(XRDYAsynchH)
t
su(XRDYAsynchH)XCOHL
t
h(XRDYAsynchH)XZCSH
(1)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip-select high
11
0
11
8
3
MAX
UNIT
ns
ns
ns
ns
ns
The first XREADY (asynchronous) sample occurs with respect to E in
E = (XRDLEAD + XRDACTIVE – 2) t
c(XTIM)
When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found
to be low, it will be sampled again each t
c(XTIM)
until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) t
c(XTIM)
– t
su(XRDYAsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
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Electrical Specifications
133
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