SPRS174S – APRIL 2001 – REVISED MARCH 2011
www.ti.com
6.24 External Interface Read Timing
Table 6-32. External Memory Interface Read Switching Characteristics
PARAMETER
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
d(XCOHL-XRDL)
t
d(XCOHL-XRDH)
t
h(XA)XZCSH
t
h(XA)XRD
(1)
Delay time, XCLKOUT high to zone chip-select active-low
Delay time, XCLKOUT high/low to zone chip-select inactive-high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active-low
Delay time, XCLKOUT high/low to XRD inactive-high
Hold time, address valid after zone chip-select inactive-high
Hold time, address valid after XRD inactive-high
–2
(1)
(1)
MIN
–2
MAX
1
3
2
1
1
UNIT
ns
ns
ns
ns
ns
ns
ns
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6-33. External Memory Interface Read Timing Requirements
MIN
t
a(A)
t
a(XRD)
t
su(XD)XRD
t
h(XD)XRD
(1)
Access time, read data from address valid
Access time, read data valid from XRD active-low
Setup time, read data valid before XRD strobe inactive-high
Hold time, read data valid after XRD inactive-high
12
0
MAX
(LR + AR) – 14
(1)
AR – 12
(1)
UNIT
ns
ns
ns
ns
LR = Lead period, read access. AR = Active period, read access. See
130
Electrical Specifications
Copyright © 2001–2011, Texas Instruments Incorporated
Product Folder Link(s):
TI [ TEXAS INSTRUMENTS ]
