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SPRS174S – APRIL 2001 – REVISED MARCH 2011
Table 6-29. SPI Slave Mode External Timing (Clock Phase = 1)
(1) (2)
NO.
12
13
14
(3)
MIN
t
c(SPC)S
t
w(SPCH)S
t
w(SPCL)S
t
w(SPCL)S
t
w(SPCH)S
t
su(SOMI-SPCH)S
t
su(SOMI-SPCL)S
t
v(SPCH-SOMI)S
t
v(SPCL-SOMI)S
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
8t
c(LCO)
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
– 10
0.125t
c(SPC)S
0.125t
c(SPC)S
0.75t
c(SPC)S
0.75t
c(SPC)S
0
0
0.5t
c(SPC)S
0.5t
c(SPC)S
MAX
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
UNIT
ns
ns
ns
ns
ns
(3)
17
(3)
18
(3)
21
(3)
22
(3)
t
su(SIMO-SPCH)S
t
su(SIMO-SPCL)S
t
v(SPCH-SIMO)S
t
v(SPCL-SIMO)S
ns
ns
(1)
(2)
(3)
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
t
c(SPC)
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
t
c(LCO)
= LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE:
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
• Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX.
• Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX.
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
123
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