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SPRS174S – APRIL 2001 – REVISED MARCH 2011
Table 6-26. SPI Master Mode External Timing (Clock Phase = 0)
(1) (2)
NO.
1
2
(3)
t
c(SPC)M
t
w(SPCH)M
t
w(SPCL)M
t
w(SPCL)M
3
(3)
t
w(SPCH)M
t
d(SPCH-SIMO)M
4
(3)
t
d(SPCL-SIMO)M
t
v(SPCL-SIMO)M
5
(3)
t
v(SPCH-SIMO)M
t
su(SOMI-SPCL)M
8
(3)
t
su(SOMI-SPCH)M
t
v(SPCL-SOMI)M
9
(3)
t
v(SPCH-SOMI)M
Cycle time, SPICLK
Pulse duration, SPICLK high
(clock polarity = 0)
Pulse duration, SPICLK low
(clock polarity = 1)
Pulse duration, SPICLK low
(clock polarity = 0)
Pulse duration, SPICLK high
(clock polarity = 1)
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
MIN
4t
c(LCO)
0.5t
c(SPC)M
– 10
0.5t
c(SPC)M
– 10
0.5t
c(SPC)M
– 10
0.5t
c(SPC)M
– 10
–10
–10
0.5t
c(SPC)M
– 10
0.5t
c(SPC)M
– 10
0
0
0.25t
c(SPC)M
– 10
0.25t
c(SPC)M
– 10
MAX
128t
c(LCO)
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(SPC)M
10
10
SPI WHEN (SPIBRR + 1) IS ODD AND
SPIBRR > 3
MIN
5t
c(LCO)
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10
–10
–10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
– 10
0
0
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10
0.5t
c(SPC)M
– 0.5t
c(LCO)
– 10
ns
ns
ns
MAX
127t
c(LCO)
0.5t
c(SPC)M
– 0.5t
c(LCO)
0.5t
c(SPC)M
– 0.5t
c(LCO)
0.5t
c(SPC)M
+ 0.5t
c(LCO)
0.5t
c(SPC)M
+ 0.5t
c(LCO)
10
10
ns
ns
ns
ns
UNIT
(1)
(2)
(3)
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
t
c(SPC)
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
t
c(LCO)
= LSPCLK cycle time
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE:
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
• Master mode transmit: 20 MHz MAX. Master mode receive: 12.5 MHz MAX.
• Slave mode transmit: 12.5 MHz MAX. Slave mode receive: 12.5 MHz MAX.
Copyright © 2001–2011, Texas Instruments Incorporated
Electrical Specifications
117
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