TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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operands, instructions were also added to double the number of these conversions that can be done. The .L unit also
has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of
complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the
conjugate of a complex number.
The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a DSP stall
until the completion of all the DSP-triggered memory transactions, including:
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•
•
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Cache line fills
Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints
Victim write backs
Block or global coherence operations
Cache mode changes
Outstanding XMC prefetch requests
This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides
ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that
depend on ordering, and manual coherence operations.
For more details on the C66x DSP and its enhancements over the C64x+ and C674x architectures, see the following
documents:
•
C66x CPU and Instruction Set Reference Guide in ‘‘Related Documentation from Texas Instruments’’ on
page 73.
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•
C66x DSP Cache User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
C66x CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
Copyright 2013 Texas Instruments Incorporated
Device Overview 19
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