TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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4.3 Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority
registers allow software configuration of the data traffic through the TeraNet. Note that a lower number means
higher priority - PRI = 000b = urgent, PRI = 111b = low.
All other masters provide their priority directly and do not need a default priority setting. Examples include the
CorePacs, whose priorities are set through software in the UMC control registers. All the packet-DMA-based
peripherals also have internal registers to define the priority level of their initiated transactions.
The packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The
priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in Figure 4-5 and
Table 4-4.
Figure 4-5
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)
31
3
2
0
Reserved
PKTDMA_PRI
RW-000
R/W-00000000000000000000001000011
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4-4
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
Bit
Field
Description
31-3
2-0
Reserved
Reserved.
PKDTDMA_PRI
Control the priority level for the transactions from packet DMA master port, which access the external linking RAM.
End of Table 4-4
For all other modules, see the respective User Guides in “Related Documentation from Texas Instruments” on
page 73 for programmable priority registers.
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System Interconnect 107
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