TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, UCD9501
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
www.ti.com
SPRS230H–OCTOBER 2003–REVISED JUNE 2006
The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1
to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO
register mapping.
Table 4-15. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
0x6F80
0x6F82
0x6F84
0x6F86
0x6F88
0x6F8A
0x6F8C
2
2
2
2
2
2
2
GPIO A Control Register (GPIO0 to 31)
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
GPIO A MUX 2 Register (GPIO16 to 31)
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPAPUD
0x6F8E
0x6F8F
reserved
2
GPBCTRL
GPBQSEL1
GPBQSEL2
GPBMUX1
GPBMUX2
GPBDIR
0x6F90
0x6F92
0x6F94
0x6F96
0x6F98
0x6F9A
0x6F9C
2
2
2
2
2
2
2
GPIO B Control Register (GPIO32 to 35)
GPIO B Qualifier Select 1 Register (GPIO32 to 35)
reserved
GPIO B MUX 1 Register (GPIO32 to 35)
reserved
GPIO B Direction Register (GPIO32 to 35)
GPIO B Pull Up Disable Register (GPIO32 to 35)
GPBPUD
0x6F9E
0x6F9F
reserved
reserved
2
reserved
0x6FA0
0x6FBF
32
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
GPASET
0x6FC0
0x6FC2
0x6FC4
0x6FC6
0x6FC8
0x6FCA
0x6FCC
0x6FCE
2
2
2
2
2
2
2
2
GPIO Data Register (GPIO0 to 31)
GPIO Data Set Register (GPIO0 to 31)
GPIO Data Clear Register (GPIO0 to 31)
GPIO Data Toggle Register (GPIO0 to 31)
GPIO Data Register (GPIO32 to 35)
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPIO Data Set Register (GPIO32 to 35)
GPIO Data Clear Register (GPIO32 to 35)
GPIO Data Toggle Register (GPIO32 to 35)
GPBCLEAR
GPBTOGGLE
0x6FD0
0x6FDF
reserved
16
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
0x6FE0
0x6FE1
0x6FE2
1
1
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XNMI GPIO Input Select Register (GPIO0 to 31)
0x6FE3
0x6FE7
reserved
GPIOLPMSEL
reserved
5
2
0x6FE8
LPM GPIO Select Register (GPIO0 to 31)
0x6FEA
0x6FFF
22
80
Peripherals
TI [ TEXAS INSTRUMENTS ]
