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TMS320F2809 参数 Datasheet PDF下载

TMS320F2809图片预览
型号: TMS320F2809
PDF下载: 下载PDF文件 查看货源
内容描述: - 12号的铝制车身绘( RAL 7032 ) []
分类和应用:
文件页数/大小: 134 页 / 1127 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TMS320F2809, TMS320F2808, TMS320F2806  
TMS320F2802, TMS320F2801, UCD9501  
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs  
www.ti.com  
SPRS230HOCTOBER 2003REVISED JUNE 2006  
Table 6-21. HALT Mode Switching Characteristics  
PARAMETER  
MIN  
TYP  
MAX  
45tc(SCO)  
UNIT  
cycles  
cycles  
td(IDLE-XCOL)  
Delay time, IDLE instruction executed to XCLKOUT low  
PLL lock-up time  
32tc(SCO)  
tp  
131072tc(OSCCLK)  
Delay time, PLL lock to program execution resume  
1125tc(SCO)  
35tc(SCO)  
cycles  
cycles  
Wake up from flash  
Flash module in sleep state  
td(WAKE-HALT)  
Wake up from SARAM  
(G)  
(A)  
(C)  
(E)  
(B)  
(D)  
HALT  
(F)  
Device  
Status  
HALT  
Flushing Pipeline  
PLL Lock-up Time  
Normal  
Execution  
Wake-up Latency  
GPIOn  
t
d(WAKE−HALT)  
t
w(WAKE-GPIO)  
t
p
X1/X2  
or XCLKIN  
Oscillator Start-up Time  
XCLKOUT  
t
d(IDLE−XCOL)  
A. IDLE instruction is executed to put the device into HALT mode.  
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator is  
turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending  
operations to flush properly.  
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as  
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes  
absolute minimum power.  
D. When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The  
GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock  
signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup  
procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.  
E. When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or  
XCLKIN) cycles.  
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT  
mode is now exited.  
G. Normal operation resumes.  
Figure 6-13. HALT Wake-Up Using GPIOn  
Electrical Specifications  
107