GENERAL CALL
The TMP175 and TMP75 respond to a Two-Wire General
Call address (0000000) if the eighth bit is 0. The device will
acknowledge the General Call address and respond to com-
mands in the second byte. If the second byte is 00000100,
the TMP175 and TMP75 will latch the status of their address
pins, but will not reset. If the second byte is 00000110, the
TMP175 and TMP75 will latch the status of their address pins
and reset their internal registers to their power-up values.
TIMING DIAGRAMS
The TMP175 and TMP75 are Two-Wire and SMBus compat-
ible. Figures 4 to 8 describe the various operations on the
TMP175 and TMP75. Bus definitions are given below. Pa-
rameters for Figure 4 are defined in Table XIII.
Bus Idle:
Both SDA and SCL lines remain HIGH.
Start Data Transfer:
A change in the state of the SDA line,
from HIGH to LOW, while the SCL line is HIGH, defines a
START condition. Each data transfer is initiated with a
START condition.
Stop Data Transfer:
A change in the state of the SDA line
from LOW to HIGH while the SCL line is HIGH defines a
STOP condition. Each data transfer is terminated with a
repeated START or STOP condition.
Data Transfer:
The number of data bytes transferred be-
tween a START and a STOP condition is not limited and is
determined by the master device. The receiver acknowl-
edges the transfer of data.
Acknowledge:
Each receiving device, when addressed, is
obliged to generate an Acknowledge bit. A device that
acknowledges must pull down the SDA line during the
Acknowledge clock pulse in such a way that the SDA line is
stable LOW during the HIGH period of the Acknowledge
clock pulse. Setup and hold times must be taken into ac-
count. On a master receive, the termination of the data
transfer can be signaled by the master generating a Not-
Acknowledge on the last byte that has been transmitted by
the slave.
HIGH-SPEED MODE
In order for the Two-Wire bus to operate at frequencies
above 400kHz, the master device must issue an Hs-mode
master code (00001XXX) as the first byte after a START
condition to switch the bus to high-speed operation. The
TMP175 and TMP75 will not acknowledge this byte, but will
switch their input filters on SDA and SCL and their output
filters on SDA to operate in Hs-mode, allowing transfers at up
to 3.4MHz. After the Hs-mode master code has been issued,
the master will transmit a Two-Wire slave address to initiate
a data transfer operation. The bus will continue to operate in
Hs-mode until a STOP condition occurs on the bus. Upon
receiving the STOP condition, the TMP175 and TMP75 will
switch the input and output filter back to fast-mode operation.
TIMEOUT FUNCTION
The TMP175 and TMP75 will reset the serial interface if
either SCL or SDA are held low for 54ms (typ) between a
START and STOP condition. The TMP175 and TMP75 will
release the bus if it is pulled low and will wait for a start
condition. The timeout function requires a communication
speed of at least 1kHz for SCL operating frequency.
FAST MODE
PARAMETER
SCL Operating Frequency
Bus Free Time Between STOP and START Condition
Hold Time After Repeated START Condition.
After this period, the first clock is generated.
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock LOW Period
SCL Clock HIGH Period
Clock/Data Fall Time
Clock/Data Rise Time
f
(SCL)
t
(BUF)
t
(HDSTA)
t
(SUSTA)
t
(SUSTO)
t
(HDDAT)
t
(SUDAT)
t
(LOW)
t
(HIGH)
t
F
t
R
MIN
0.001
600
100
100
100
0
100
1300
600
300
300
MAX
0.4
HIGH-SPEED MODE
MIN
0.001
160
100
100
100
0
10
160
60
160
160
MAX
3.4
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TABLE XIII. Timing Diagram Definitions for TMP175 and TMP75.
TMP175, 75
SBOS288C
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