TMP175
TMP75
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SBOS288J − JANUARY 2004 − REVISED DECEMBER 2007
TIMING DIAGRAMS
The TMP175 and TMP75 are Two-Wire and SMBus
compatible. Figure 4 to Figure 8 describe the various
operations on the TMP175 and TMP75. Bus definitions are
given below. Parameters for Figure 4 are defined in
Table 13.
Bus Idle:
Both SDA and SCL lines remain HIGH.
Start Data Transfer:
A change in the state of the SDA line,
from HIGH to LOW, while the SCL line is HIGH, defines a
START condition. Each data transfer is initiated with a
START condition.
Stop Data Transfer:
A change in the state of the SDA line
from LOW to HIGH while the SCL line is HIGH defines a
STOP condition. Each data transfer is terminated with a
repeated START or STOP condition.
Data Transfer:
The number of data bytes transferred
between a START and a STOP condition is not limited and
is determined by the master device. The receiver
acknowledges the transfer of data.
Acknowledge:
Each receiving device, when addressed,
is obliged to generate an Acknowledge bit. A device that
acknowledges must pull down the SDA line during the
Acknowledge clock pulse in such a way that the SDA line
is stable LOW during the HIGH period of the Acknowledge
clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data
transfer can be signaled by the master generating a
Not-Acknowledge on the last byte that has been
transmitted by the slave.
PARAMETER
SCL Operating Frequency
Bus Free Time Between STOP and START Condition
Hold time after repeated START condition.
After this period, the first clock is generated.
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock LOW Period
SCL Clock HIGH Period
Clock/Data Fall Time
Clock/Data Rise Time
for SCLK
≤
100kHz
f(SCL)
t(BUF)
t(HDSTA)
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
tF
tR
tR
FAST MODE
MIN
0.001
600
100
100
100
0
100
1300
600
300
300
1000
MAX
0.4
HIGH-SPEED MODE
MIN
0.001
160
100
100
100
0
10
160
60
160
160
MAX
3.4
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 13. Timing Diagram Definitions for the TMP175 and TMP75
TWO-WIRE TIMING DIAGRAMS
t
(LOW)
t
R
t
F
t
(HDSTA)
SCL
t
(HDSTA)
t
(HDDAT)
SDA
t
(BU F )
P
S
S
P
t
(HIGH)
t
(SUSTA)
t
(SUDAT)
t
(SUSTO)
Figure 4. Two-Wire Timing Diagram
10
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