TMDS361B
www.ti.com
SLLS988A –SEPTEMBER 2009–REVISED JULY 2011
DISSIPATION RATINGS
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
PACKAGE
PCB JEDEC STANDARD
TA ≤ 25°C
Low-K
High-K
1066 mW
1481 mW
10.66 mW/°C
586 mW
814 mW
64-pin TQFP (PAG)
14.8 mW/°C
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX(1) UNIT
°C/W
RθJB
RθJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
37.13
15.3
°C/W
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps
PD(1)
Device power dissipation in normal mode TMDS data pattern; HPD_SINK = HIGH,
S1/S2 = LOW/LOW, LOW/HIGH, HIGH/HIGH
560
780
mW
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps
Device power dissipation in standby
TMDS data pattern; HPD_SINK = HIGH,
mode
PD(2)
10
1
20
2
mW
mW
S1 = HIGH, S2 = LOW
Device power dissipation in low-power
PSD
LP = LOW
mode
LP = HIGH, no TMDS input clock,
Device power dissipation in normal mode
HPD_SINK =HIGH, S1/S2 = LOW/LOW,
with no active TMDS input clock
PNCLK
TJ
40
65
mW
LOW/HIGH, HIGH/HIGH
Junction Temperature
0
125
°C
(1) The maximum rating is simulated under 3.6-V VCC across worst-case temperature and process variation. Typical conditions are
simulated at 3.3-V VCC, 25°C with nominal process material.
RECOMMENDED OPERATING CONDITIONS
MIN
3
NOM
MAX UNIT
VCC
TA
Supply voltage
3.3
3.6
70
V
Operating free-air temperature
0
°C
TMDS DIFFERENTIAL OUTPUT AND INPUT PINS
VID(pp)
VIC
Peak-to-peak input differential voltage
Input common-mode voltage
0.15
VCC – 0.4
75
1.56
V
V
VCC + 0.01
tIN_Rise_Fall
TMDS input rise and fall time
ps
Acceptable pre-emphasis on TMDS input signals. Note that an input
signal into TMDS361B with longer pre-emphasis duration and/or larger
pre-emphasis amplitude could result in over-equalization.
VIN_PRE
See (Figure 26)
3.3
AVCC
dR
TMDS output termination voltage
Data rate
3
3.6
3
V
Gbps
kΩ
RVSadj
RT
Resistor for TMDS-compliant voltage output swing
Termination resistance
3.66
45
4.02
50
4.47
55
Ω
DDC PINS
VI
Input voltage
I2C data rate
0
5.5
V
dR(I2C)
100 Kbps
HPD AND CONTROL PINS
VIH
VIL
High-level input voltage
Low-level input voltage
2
0
5.5
0.8
V
V
Copyright © 2009–2011, Texas Instruments Incorporated
9
TI [ TEXAS INSTRUMENTS ]
