2.4.3 Three-Wire Control Interface (SDIN)
PARAMETER
MIN
20
20
80
60
20
20
20
20
TYP
MAX
UNIT
t
t
t
t
t
t
t
t
High
Low
w(5)
w(6)
c(3)
Clock pulse duration, SCLK
Clock period, SCLK
ns
ns
ns
ns
ns
Clock rising edge to CS rising edge, SCLK
Setup time, SDIN to SCLK
Hold time, SCLK to SDIN
High
su(4)
su(5)
h(4)
w(7)
w(8)
ns
Pulse duration, CS
Low
t
w(8)
CS
t
c(3)
t
t
t
su(4)
w(5)
w(6)
SCLK
DIN
t
t
h(4)
su(5)
LSB
Figure 2−4. Three-Wire Control Interface Timing Requirements
2.4.4 Two-Wire Control Interface
PARAMETER
High
Low
MIN
1.3
600
0
TYP
MAX
400
UNIT
µs
t
t
w(9)
Clock pulse duration, SCLK
ns
w(10)
f(sf)
Clock frequency, SCLK
Hold time (start condition)
Setup time (start condition)
Data hold time
kHz
ns
t
t
t
t
t
t
t
t
600
600
h(5)
su(6)
h(6)
su(7)
r
ns
900
ns
Data setup time
100
ns
Rise time, SDIN, SCLK
Fall time, SDIN, SCLK
Setup time (stop condition)
300
300
ns
ns
f
600
0
ns
su(8)
sp
Pulse width of spikes suppressed by input filter
50
ns
t
t
t
w(10)
sp
w(9)
SCLK
t
t
t
t
su(8)
h(5)
h(6)
su(7)
DIN
Figure 2−5. Two-Wire Control Interface Timing Requirements
2−7
TI [ TEXAS INSTRUMENTS ]
