2.4 Digital-Interface Timing
PARAMETER
tw(1)
tw(2)
tc(1)
tpd(1)
High
System-clock pulse duration, MCLK/XTI
System-clock period, MCLK/XTI
Duty cycle, MCLK/XTI
Propagation delay, CLKOUT
Low
MIN
18
18
54
40/60%
0
60/40%
10
ns
ns
ns
TYP
MAX
UNIT
tc(1)
tw(1)
MCLK/XTI
tpd(1)
CLKOUT
tw(2)
CLKOUT
(Div 2)
Figure 2−1. System-Clock Timing Requirements
2.4.1
tpd(2)
tpd(3)
tsu(1)
th(1)
Audio Interface (Master Mode)
PARAMETER
Propagation delay, LRCIN/LRCOUT
Propagation delay, DOUT
Setup time, DIN
Hold time, DIN
MIN
0
0
10
10
TYP
MAX
10
10
UNIT
ns
ns
ns
ns
BCLK
tpd(2)
LRCIN
LRCOUT
tpd(3)
DOUT
DIN
tsu(1)
th(1)
Figure 2−2. Master-Mode Timing Requirements
2−5