Sample Rate Control (Address: 0001000)
BIT
Function
Default
D8
X
0
D7
CLKOUT
0
D6
CLKIN
0
D5
SR3
1
D4
SR2
0
D3
SR1
0
D2
SR0
0
D1
BOSR
0
D0
USB/Normal
0
CLKIN
CLKOUT
SR[3:0]
BOSR
USB/Normal
X
BIT
Function
Default
D8
X
0
Clock input divider
0 = MCLK
1 = MCLK/2
Clock output divider
0 = MCLK
1 = MCLK/2
Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2)
Base oversampling rate
USB mode:
0 = 250 f
s
1 = 272 f
s
Normal mode:
0 = 256 f
s
1 = 384 f
s
Clock mode select:
0 = Normal
1 = USB
Reserved
D7
RES
0
D6
RES
0
D5
X
0
D4
X
0
D3
X
0
D2
X
0
D1
X
0
D0
ACT
0
Digital Interface Activation (Address: 0001001)
ACT
X
BIT
Function
Default
D8
RES
0
Activate interface
Reserved
D7
RES
0
D6
RES
0
0 = Inactive
1 = Active
Reset Register (Address: 0001111)
D5
RES
0
D4
RES
0
D3
RES
0
D2
RES
0
D1
RES
0
D0
RES
0
RES
Write 000000000 to this register triggers reset
3.2 Analog Interface
3.2.1
Line Inputs
The TLV320AIC23B has line inputs for the left and the right audio channels (RLINEIN and LLINEIN). Both line inputs
have independently programmable volume controls and mutes. Active and passive filters for the two channels
prevent high frequencies from folding back into the audio band.
The line-input gain is logarithmically adjustable from 12 dB to –34.5 dB in 1.5-dB steps. The ADC full-scale range
is 1.0 V
RMS
at AV
DD
= 3.3 V. The full-scale range tracks linearly with analog supply voltage AV
DD
. To avoid distortions,
it is important not to exceed the full-scale range.
The gain is independently programmable on both left and right line-inputs. To reduce the number of software write
cycles required. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3).
The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode,
the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise
might be heard when reactivating the inputs.
For interfacing to a CD system, the line input should be scaled to 1 V
RMS
to avoid clipping, using the circuit shown
in Figure 3-3.
Where:
R1 = 5 kΩ
R2 = 5 kΩ
C1 = 47 pF
C2 = 470 nF
CDIN
R
2
AGND
C1
R1
C2
+
LINEIN
Figure 3−3. Analog Line Input Circuit
R1 and R2 divide the input signal by two, reducing the 2 V
RMS
from the CD player to the nominal 1 V
RMS
of the AIC23B
inputs. C1 filters high-frequency noise, and C2 removes any dc component from the signal.
3−5
TI [ TEXAS INSTRUMENTS ]
