TLC5620C, TLC5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001
electrical characteristics over recommended operating free-air temperature range, V
DD
= 5 V
±
5%,
V
ref
= 2 V,
×
1 gain output range (unless otherwise noted)
PARAMETER
IIH
IIL
IO(sink)
IO(source)
Ci
IDD
Iref
EL
ED
EZS
EFS
PSRR
High-level input current
Low-level input current
Output sink current
Output source current
Input capacitance
Reference input capacitance
Supply current
Reference input current
Linearity error (end point corrected)
Differential-linearity error
Zero-scale error
Zero-scale-error temperature coefficient
Full-scale error
Full-scale-error temperature coefficient
Power-supply rejection ratio
VDD = 5 V
VDD = 5 V,
Vref = 2 V,
Vref = 2 V,
Vref = 2 V,
Vref = 2 V,
Vref = 2 V,
Vref = 2 V,
Vref = 2 V
×
2 gain (see Note 1)
×
2 gain (see Note 2)
×
2 gain (see Note 3)
×
2 gain (see Note 4)
×
2 gain (see Note 5)
×
2 gain (see Note 6)
±
25
0.5
0
10
±
60
TEST CONDITIONS
VI = VDD
VI = 0 V
Each DAC output
20
2
15
15
2
±
10
±
1
±
0.9
30
MIN
TYP
MAX
±
10
±
10
UNIT
µA
µA
µA
mA
pF
mA
µA
LSB
LSB
mV
µV/°C
mV
µV/°C
mV/V
See Notes 7 and 8
NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full-scale errors).
2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
4. Zero-scale-error temperature coefficient is given by: ZSETC = [ZSE(Tmax) – ZSE(Tmin)]/Vref
×
106/(Tmax – Tmin).
5. Full-scale error is the deviation from the ideal full-scale output (Vref – 1 LSB) with an output load of 10 kΩ.
6. Full-scale-error temperature coefficient is given by: FSETC = [FSE(Tmax) – FSE (Tmin)]/Vref
×
106/(Tmax – Tmin).
7. Zero-scale-error rejection ratio (ZSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
8. Full-scale-error rejection ratio (FSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the full-scale output voltage.
operating characteristics over recommended operating free-air temperature range, V
DD
= 5 V
±
5%,
V
ref
= 2 V,
×
1 gain output range (unless otherwise noted)
TEST CONDITIONS
Output slew rate
Output settling time
Large-signal bandwidth
Digital crosstalk
Reference feedthrough
Channel-to-channel isolation
Reference input bandwidth
CL = 100 pF,
To
±
0.5 LSB,
RL = 10 kΩ
CL = 100 pF,
RL = 10 kΩ,
See Note 9
MIN
TYP
1
10
100
– 50
– 60
– 60
100
MAX
UNIT
V/µs
µs
kHz
dB
dB
dB
kHz
Measured at – 3 dB point
CLK = 1-MHz square wave measured at DACA-DACD
See Note 10
See Note 11
See Note 12
NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full scale voltage within +/– 0.5 LSB starting from
an initial output voltage equal to zero.
10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 Vpp at 10 kHz.
11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with Vref input = 1 V dc + 1 Vpp at 10 kHz.
12. Reference bandwidth is the –3 dB bandwidth with an input at Vref = 1.25 V dc + 2 Vpp and with a full-scale digital-input code.
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