TLC5615C, TLC5615I
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142C – OCTOBER 1996 – REVISED MARCH 2000
APPLICATION INFORMATION
serial interface
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most
significant bit first. The rising edge of the SLCK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot beclocked
into the input register. All CS transitions should occur when the SCLK input is low.
If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data
sequence with the MSB first can be used as shown in Figure 10:
12 Bits
10 Data Bits
x
x
MSB
LSB
2 Extra (Sub-LSB) Bits
x = don’t care
Figure 10. 12-Bit Input Data Sequence
or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.
16 Bits
4 Upper Dummy Bits
10 Data Bits
x
x
MSB
LSB
2 Extra (Sub-LSB) Bits
x = don’t care
Figure 11. 16-Bit Input Data Sequence
The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width.
When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data
transfer requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the
DOUT terminal (see Figure 1).
Thetwoextra(sub-LSB)bitsarealwaysrequiredtoprovidehardwareandsoftwarecompatibilitywith12-bitdata
converter transfers.
†
The TLC5615 three-wire interface is compatible with the SPI, QSPI , and Microwire serial standards. The
hardware connections are shown in Figure 12 and Figure 13.
The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input
data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC
input register in one write cycle.
†
CPOL = 0, CPHA = 0, QSPI protocol designations
12
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