TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
recommended operating conditions
PARAMETER
Supply voltage VDD (each supply, see Note 3)
supply
voltage,
Input voltage, VI (inputs except VCO IN)
Output current, IO (each output)
VCO control voltage at VCO IN
Lock frequency (×1 output)
Lock frequency (×1/2 output)
Bias resistor, RBIAS
resistor
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
MIN
2.85
4.75
0
0
0.9
14
22
7
11
2.2
1.5
3.3
2.2
NOM
3
5
MAX
3.15
5.25
VDD
±
2
VDD
21
50
10.5
25
4.3
3.3
UNIT
V
V
mA
V
MHz
MHz
kΩ
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage
and separated from each other.
electrical characteristics over recommended operating free-air temperature range, V
DD
= 3 V
(unless otherwise noted)
VCO section
PARAMETER
VOH
VOL
VIT
II
Zi(VCO IN)
IDD(INH)
High-level output voltage
Low-level output voltage
Input threshold voltage at SELECT, VCO INHIBIT
Input current at SELECT, VCO INHIBIT
Input impedance
VCO supply current (inhibit)
VI = VDD or GND
VCO IN = 1/2 VDD
See Note 4
TEST CONDITIONS
IOH = – 2 mA
IOL = 2 mA
MIN
2.4
0.3
0.9
1.5
10
0.01
1
15
2.1
±
1
TYP
MAX
UNIT
V
V
V
µA
MΩ
µA
mA
IDD(VCO)
VCO supply current
See Note 5
5
NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited.
5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.
PFD section
PARAMETER
VOH
VOL
IOZ
VIH
VIL
VIT
Ci
Zi
IDD(Z)
High-level output voltage
Low-level output voltage
High-impedance-state output current
High-level input voltage at FIN–A, FIN–B
Low-level input voltage at FIN–A, FIN–B
Input threshold voltage at PFD INHIBIT
Input capacitance at FIN–A, FIN–B
Input impedance at FIN–A, FIN–B
High-impedance-state PFD supply current
See Note 6
0.9
1.5
5
10
0.01
1
TEST CONDITIONS
IOH = – 2 mA
IOL = 2 mA
PFD INHIBIT = high,
VI = VDD or GND
2.7
0.5
2.1
MIN
2.7
0.2
±
1
TYP
MAX
UNIT
V
V
µA
V
V
V
pF
MΩ
µA
IDD(PFD) PFD supply current
See Note 7
0.1
1.5
mA
NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.
7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (VI(PP) = 3 V, rectangular wave), NC = GND, no load, and VCO OUT is
inhibited.
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•
DALLAS, TEXAS 75265
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TI [ TEXAS INSTRUMENTS ]
