TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
PRINCIPLES OF OPERATION
†
register map
Each register is selected using address lines A[0], A[1], A[2] and, in some cases, bits from other registers. The
programming combinations for register selection are shown in Table 7. All registers shown in bold are accessed
by a combination of address pins and register bits.
Table 7. Register Map – Read/Write Properties
A[2]
0
A[1]
0
A[0]
0
READ MODE
Receive holding register (RHR)
Interrupt enable register (IER)
Interrupt identification register (IIR)
Line control register (LCR)
Modem control register (MCR)
Line status register (LSR)
Modem status register (MSR)
Scratch register (SPR)
WRITE MODE
Transmit holding register (THR)
Interrupt enable register
0
0
1
0
1
0
FIFO control register (FCR)
Line control register
0
1
1
1
0
0
Modem control register
1
0
1
1
1
0
1
1
1
Scratch register (SPR)
Divisor latch LSB (DLL)
Divisor latch MSB (DLH
Enhanced feature register
Xon-1 word
0
0
0
Divisor latch LSB (DLL)
Divisor latch MSB (DLH)
Enhanced feature register (EFR)
Xon-1 word
0
0
1
0
1
0
1
0
0
1
0
1
Xon-2 word
Xon-2 word
1
1
0
Xoff-1 word
Xoff-1 word
1
1
1
Xoff-2 word
Xoff-2 word
1
1
0
Transmission control register (TCR)
Trigger level register (TLR)
FIFO ready register
Transmission control register
Trigger level register
1
1
1
1
1
1
†
DLL and DLH are accessible only when LCR bit-7, is 1.
Enhanced feature register, Xon1, 2 and Xoff1, 2 are accessible only when LCR is set to 10111111 (8hBF).
Transmission control register and trigger level register are accessible only when EFR[4] = 1 and MCR[6] = 1, i.e.. EFR[4] and MCR[6] are
read/write enables.
FIFORdy register is accessible only when CSA and CSB = 0, MCR [2] = 1 and loopback is disabled (MCR[4]=0).
MCR[7] can only be modified when EFR[4] is set.
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