TL16C752B
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS405A – DECEMBER 1999 – REVISED AUGUST 2000
Start
Bit
Stop
Bit
Data Bits (5–8)
D3 D4
D0
D1
D2
D5
D6
D7
TX (A–B)
Parity
Bit
5 Data Bits
6 Data Bits
7 Data Bits
Active
IOW
D0–D7
Byte 32
t
d18
t
d17
TXRDY (A–B)
Trigger
Lead
Figure 20. Transmit Ready Timing in FIFO Mode
timing error condition
Texas Instruments has discovered a timing anomaly in two of its newest products in the UART family, namely
the TL16C752 and TL16C752B.
The problem only occurs under a special set of circumstances (non-FIFO mode), and can be worked around
by using certain timing. Depending on actual system application, some customers may not see this problem.
There are currently no plans to fix this problem because it is felt that it is a minor issue. It is unlikely the device
will be used in non-FIFO mode, and if it is, the software workaround will not have a significant impact on
throughput, < 1%.
problem description
When using the non-FIFO (single byte) mode of operation, it is possible that valid data could be reported as
available by either the line status register (LSR) or the interrupt identification register (IIR), before the receiver
holding register (RHR) can be read. In other words, the loading of valid data in RHR may be delayed when the
part operates in non-FIFO mode. The data in the RHr will be valid after a delay of one baud-clock period after
the update of the LSR or IIR. The baud-clock runs at 16X the baudrate. The following table is a sample of baud
rates and associated required delays. Depending on the operating environment, this time may well be
transparent to the system, e.g., less than the context switch time of the interrupt service routine.
A similar problem does not exist when using FIFO mode (64 byte) mode of operation.
BAUDRATE (BIT PER-SECOND)
REQUIRED DELAY (µs)
1200
2400
52.1 µs
26 µs
4800
13 µs
9600
6.5 µs
3.3 µs
1.6 µs
1.1 µs
0.5 µs
62.5 ns
19200
38400
57600
115200
1000000
22
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