interpolation on the color data path. When a format with embedded sync is selected, DMAN also extracts H(Hsync),
V(Vsync),F(FieldID)identifiersfromtheITU-R.BT656(SDTV)orSMPTE274M/296M(HDTV)datastreamforinternal
synchronization of the DTG. Alternatively, the device synchronizes to HS_IN, VS_IN, FID inputs.
3.1.1 Interpolating Finite Impulse Responses Filter (IFIR)
The interpolating FIR is used to upsample the input data by 2× . In the THS82000 there are five IFIRs. The first two
are used only when the input data is in 4:2:2 format for conversion to a 4:4:4 internal representation on both color
difference channels. The last three IFIRs are used to upsample the internal data to the DACs on all three channels
in case 2× video interpolation is enabled. By 2× oversampling the video data, the requirements for the analog
reconstruction filter at the DAC outputs are relaxed so it can be built with fewer components, thereby also improving
the overall video frequency characteristic (less group delay variation). All of the IFIRs can be bypassed or switched
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in by programming the appropriate I C registers. The coefficients of all IFIRs are fixed.
3.1.2 Color-Space Conversion (CSC)
The color-space converter block is used to convert input video data in one type of color space to output video data
in another color space (e.g., RGB to YCbCr, or vice versa). This block contains a 3×3 matrix multiplier/adder and a
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3×1 adder. All multiplier and adder coefficients can be programmed via the I C interface to support any linear
matrixing+offset operation on the video data.
3.1.3 Clip/Shift/Multiplier (CSM)
Theclip-shift-multiplyblockoptionallyclipstheinputcoderangeataprogrammedlow/highcode, shiftstheinputvideo
data downwards, and multiplies the input by a programmable coefficient in the range 0–1.999. This allows for
operation with a reduced input code range such as prescribed in the ITU-R.BT601 recommendation. Each channel
can be independently programmed to accommodate different digital ranges for each of the three input channels. For
example, forstandardvideosignalstheYchannelhasadigitalinputrangeof64–940, whereasthetwootherchannels
haveaninputrangeof64–960. AllthreechannelsmusthaveaDACoutputrangeof0–700mV, sonormallytheanalog
voltage corresponding to 1 LSB would have to change to account for the different digital inputs. This might cause
matching errors. Therefore in the THS8200 the DAC LSB does not change; rather LSB conversion is done by scaling
the digital inputs to the DAC’s full input range. Furthermore, the CSM output is 11 bits wide and is sent to the 11-bit
DACs. The extra bit of resolution resolves nonlinearities introduced by the scaling process. The clipping function can
be switched off to allow for super-white/super-black excursions.
3.1.4 Digital Multiplexer (DIGMUX)
This multiplexer in front of the DACs can select between video signals at 1× or 2× the pixel clock rate. It is also used
toswitchinblanking/syncleveldatageneratedbythedisplaytiminggenerator(DTG)blockandtestpatterndata(e.g.,
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color bars, I C-controlled DAC levels) or to perform data insertion (CGMS) during vertical blanking.
3.1.5 Display Timing Generator (DTG)
The display timing generator is responsible for the generation of the correct frame format including all sync,
equalizationandserrationpulses. Inmastertimingmode, theDTGissynchronizedtoexternalsynchronizationinputs,
either from the dedicated device terminals HS_IN, VS_IN, and FID or is synchronized to the identifiers extracted from
the input data stream, as selected by the DMAN mode. In master timing mode, the DTG generates the required
field/frame format based on the externally applied pixel clock input.
When active data is not being passed to the DACs, i.e., during the horizontal/vertical blanking intervals, the DTG
generates the correct digital words for blank, sync levels and other level excursions, such as pre- and post-serration
pulses and equalization pulses.
Horizontal timings, as well as amplitudes of negative and positive sync, HDTV broad pulses and SDTV pre- and
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post-equalization and serration pulses, are all I C-programmable to accommodate, e.g., the generation of both
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