3 THS8200 Functional Overview
digbypass
dg_bias
db_bias
dr_bias
ifir
ifir
ifir
Color
Space
Convertor
Clip
Scale
Multiplier
gy_in
bcb_in
rcr_in
hs_in
dly
ifir
ifir
dg
db
dr
4:2:2 to 4:4:4
ifir12_bypass
vs_in
ifir35_bypass
sav
eav
Display
Timing
Generator
dtg_data
Three Channel DACs
dr_bias
dg_bias
db_bias
scl_in
scl_out
scl_en
databus_in
databus_out
address
2
I C
addr_en
hs_out
vs_out
Slave
sda_in
sda_out
sda_en
cscouts
ready
csmouts
do[9:0]
dlclko
digbypass
ifirouts
tstmode
arst_func_n
clkin
clk_h
dmanouts
2X
cdrv
cgen
clkin
clk_f
clk_fx2
Clock Generator
Offset Binary Signals
Figure 3–1. Functional Block Diagram
3.1 Data Manager (DMAN)
The data manager is the block that transforms the selected input video data format present on the chip input bus(es)
to an internal 10-bit three-channel representation. Supported input formats include 10/8 bit ITU-R.BT656 with
embedded sync codes, 15-/16- or 24-/30-bit RGB with external sync, 20-/16-bit SMPTE274M/296M with embedded
sync codes, as well as 20-/16-bit YCbCr 4:2:2 with external sync. The user can optionally include a 4:2:2 to 4:4:4
3–1
TI [ TEXAS INSTRUMENTS ]
