TAS5707
www.ti.com ........................................................................................................................................................................................... SLOS556–NOVEMBER 2008
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For detailed description of using audio processing features like DRC and EQ, please refer to User's Guide and
TAS570X GDE software development tool documentation. Also refer to GDE software development tool for
device data path.
I2C COMPATIBLE SERIAL CONTROL INTERFACE
The TAS5707 DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multi-byte read and write operations for status registers
and the general control registers associated with the PWM.
SERIAL INTERFACE CONTROL AND TIMING
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
2-Channel I2S (Philips Format) Stereo Input
32 Clks
32 Clks
LRCLK (Note Reversed Phase)
Right Channel
Left Channel
SCLK
SCLK
MSB
LSB
MSB
LSB
24-Bit Mode
23 22
9
5
1
8
4
0
5
1
4
1
0
23 22
19 18
15 14
9
5
1
8
4
0
5
1
4
0
1
0
20-Bit Mode
19 18
0
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 17. I2S 64-fS Format
Copyright © 2008, Texas Instruments Incorporated
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