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TAS5707 参数 Datasheet PDF下载

TAS5707图片预览
型号: TAS5707
PDF下载: 下载PDF文件 查看货源
内容描述: 具有EQ和DRC的20W立体声数字音频功率放大器 [20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC]
分类和应用: 放大器功率放大器
文件页数/大小: 55 页 / 1219 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TAS5707  
SLOS556NOVEMBER 2008........................................................................................................................................................................................... www.ti.com  
Overtemperature Protection  
The TAS5707 has over temperature-protection system. If the device junction temperature exceeds 150°C  
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the  
high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5707 recovers automatically once the  
temperature drops approximately 30°.  
Undervoltage Protection (UVP) and Power-On  
Reset (POR)  
The UVP and POR circuits of the TAS5707 fully protect the device in any power-up/down and brownout situation.  
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully  
operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and  
AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD  
pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being  
asserted low.  
SSTIMER FUNCTIONALITY  
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when  
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current  
source, and the charge time determines the rate at which the output transitions from a near zero duty cycle to the  
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is  
shutdown the drivers are tristated and transition slowly down through a 3K resistor, similarly minimizing pops and  
clicks. The shutdown transition time is independent of SSTIMER pin capacitance. Larger capacitors will increase  
the start-up time, while capacitors smaller than 2.2 nF will decrease the start-up time. The SSTIMER pin should  
be left floating for BD modulation.  
CLOCK, AUTO DETECTION, AND PLL  
The TAS5707 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)  
supports all the sample rates and MCLK rates that are defined in the clock control register.  
The TAS5707 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×  
fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section  
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the  
internal clock (DCLK) running at 512 time the PWM switching frequency.  
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock  
rates as defined in the clock control register.  
TAS5707 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect  
changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute)  
and then force PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the  
system will auto detect the new rate and revert to normal operation. During this process, the default volume will  
be restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back  
slowly (also called soft unmute) as defined in volume register (0X0E).  
SERIAL DATA INTERFACE  
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5707 DAP accepts serial data in  
16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.  
PWM Section  
The TAS5707 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high  
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to  
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP  
and outputs two BTL PWM audio output channels.  
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff  
frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be  
enabled and disabled.  
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Copyright © 2008, Texas Instruments Incorporated  
Product Folder Link(s): TAS5707