TAS5727
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SLOS670 –NOVEMBER 2010
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.
Table 15. Channel Interchannel Delay Register Format
BITS DEFINITION
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
–
D0
–
FUNCTION
Minimum absolute delay, 0 DCLK cycles
Maximum positive delay, 31 × 4 DCLK cycles
Maximum negative delay, –32 × 4 DCLK cycles
Reserved
0
1
1
1
1
1
–
–
1
0
0
0
0
0
–
–
0
0
SUBADDRESS
0x11
D7
1
D6
0
D5
1
D4
0
D3
1
D2
1
D1
–
D0 Delay = (value) × 4 DCLKs
–
–
–
–
Default value for channel 1(1)
Default value for channel 2(1)
Default value for channel 1(1)
Default value for channel 2(1)
0x12
0
1
0
1
0
1
–
0x13
1
0
1
0
1
1
–
0x14
0
1
0
1
0
1
–
(1) Default values are in bold.
ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk, etc.) Therefore,
appropriate ICD settings must be used. By default, the device has ICD settings for the AD mode. If used in BD
mode, then update these registers before coming out of all-channel shutdown.
MODE
0x11
0x12
0x13
0x14
AD MODE
BD MODE
AC
54
B8
60
A0
48
AC
54
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