TAS5727
SLOS670 –NOVEMBER 2010
www.ti.com
VOLUME CONFIGURATION REGISTER (0x0E)
Bits
Volume slew rate (used to control volume change and MUTE ramp rates). These bits control the
D2–D0: number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of
the I2S data as follows:
Sample rate (kHz)
8/16/32
Approximate ramp rate
125 ms/step
11.025/22.05/44.1
12/24/48
90.7 ms/step
83.3 ms/step
In two-band DRC, register 0x0A should be set to 0x30 and register 0x0E bits 6 and 5 should be set to 1.
Table 13. Volume Configuration Register (0x0E)
D7 D6 D5 D4 D3
D2
–
D1
–
D0
–
FUNCTION
1
–
–
–
–
–
–
–
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
–
–
0
1
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
–
–
0
–
–
–
–
–
Reserved(1)
–
–
–
DRC2 volume 1 (ch4) from I2C register 0x08
DRC2 volume 1 (ch4) from I2C register 0x0A(1)
DRC2 volume 2 (ch3) from I2C register 0x09
DRC2 volume 2 (ch3) from I2C register 0x0A(1)
Reserved(1)
Volume slew 512 steps (43 ms volume ramp time at 48 kHz)(1)
Volume slew 1024 steps (85-ms volume ramp time at 48 kHz)
Volume slew 2048 steps (171-ms volume ramp time at 48 kHz)
Volume slew 256 steps (21-ms volume ramp time at 48 kHz)
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
1
0
1
0
0
1
1
1
X
X
(1) Default values are in bold.
MODULATION LIMIT REGISTER (0x10)
Table 14. Modulation Limit Register (0x10)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
–
D1
–
D0
–
MODULATION LIMIT
Reserved
99.2%
–
–
–
–
–
0
0
0
–
–
–
–
–
0
0
1
98.4%
–
–
–
–
–
0
1
0
97.7%(1)
–
–
–
–
–
0
1
1
96.9%
–
–
–
–
–
1
0
0
96.1%
–
–
–
–
–
1
0
1
95.3%
–
–
–
–
–
1
1
0
94.5%
–
–
–
–
–
1
1
1
93.8%
(1) Default values are in bold.
46
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