SLOS556B – NOVEMBER 2008 – REVISED NOVEMBER 2009
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PIN FUNCTIONS
PIN
NAME
AGND
AVDD
AVSS
BST_A
BST_B
BST_C
BST_D
DVDD
DVSSO
DVSS
FAULT
NO.
30
13
9
4
43
42
33
27
17
28
14
TYPE
(1)
5-V
TOLERANT
TERMINATION
(2)
DESCRIPTION
Analog ground for power stage
3.3-V analog power supply
Analog 3.3-V supply ground
High-side bootstrap supply for half-bridge A
High-side bootstrap supply for half-bridge B
High-side bootstrap supply for half-bridge C
High-side bootstrap supply for half-bridge D
3.3-V digital power supply
Oscillator ground
Digital ground
Backend error indicator. Asserted LOW for over temperature, over
current, over voltage, and under voltage error conditions. De-asserted
upon recovery from error condition.
Analog ground for power stage
Gate drive internal regulator output
P
P
P
P
P
P
P
P
P
P
DO
GND
GVDD_OUT
LRCLK
MCLK
NC
OC_ADJ
OSC_RES
OUT_A
OUT_B
OUT_C
OUT_D
PDN
29
5, 32
20
15
8
7
16
1
46
39
36
19
P
P
DI
DI
–
AO
AO
O
O
O
O
DI
5-V
Pullup
5-V
5-V
Pulldown
Pulldown
Input serial audio data left/right clock (sample rate clock)
Master clock input
No connection
Analog overcurrent programming. Requires resistor to ground.
Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO.
Output, half-bridge A
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating PWM stop
sequence.
Power ground for half-bridges A and B
Power ground for half-bridges C and D
PLL negative loop filter terminal
PLL positive loop filter terminal
Power supply input for half-bridge output A
Power supply input for half-bridge output B
Power supply input for half-bridge output C
Power supply input for half-bridge output D
PGND_AB
PGND_CD
PLL_FLTM
PLL_FLTP
PVDD_A
PVDD_B
PVDD_C
PVDD_D
RESET
47, 48
37, 38
10
11
2, 3
44, 45
40, 41
34, 35
25
P
P
AO
AO
P
P
P
P
DI
5-V
Pullup
Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard mute
state (tristated).
I
2
C serial control clock input
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
I
2
C serial control data interface input/output
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
SCL
SCLK
SDA
SDIN
24
21
23
22
DI
DI
DIO
DI
5-V
5-V
5-V
5-V
Pulldown
Pulldown
(1)
(2)
6
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups
→
logic 1 input; pulldowns
→
logic 0 input).
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