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TAS5705PAP 参数 Datasheet PDF下载

TAS5705PAP图片预览
型号: TAS5705PAP
PDF下载: 下载PDF文件 查看货源
内容描述: 具有EQ和DRC的20W立体声数字音频功率放大器 [20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC]
分类和应用: 消费电路商用集成电路音频放大器视频放大器功率放大器
文件页数/大小: 71 页 / 1403 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SLOS549 – JUNE 2008
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
SCLK
SDA
SDIN1
SDIN2
SSTIMER
NO.
23
28
25
24
6
TYPE
(1)
DI
DIO
DI
DI
AI
5-V
TOLERANT
5-V
5-V
5-V
5-V
TERMINATION
(2)
DESCRIPTION
Serial audio data clock (shift clock). SCLK is the serial audio port
input data bit clock.
I
2
C serial control data interface input/output
Serial audio data 1 input is one of the serial data input ports. SDIN1
supports three discrete (stereo) data formats.
Serial audio data 2 input is one of the serial data input ports. SDIN2
supports three discrete (stereo) data formats.
Controls ramp time of OUT_X for pop-free operation. Leave this pin
floating for BD mode. Requires capacitor of 2.2 nF to GND in AD
mode. The capacitor determines the ramp time of PWM outputs from
0% to 50%. For 2.2 nF, start/stop time is ~10 ms.
Test pin. Connect directly to GND.
Subwoofer negative PWM output
Subwoofer positive PWM output
Test pin. Connect directly to GND.
Test pin. Connect directly to DVDD.
Output indicating validity of ALL PWM channels, active-high. This pin
is connected to an external power stage. If no external power stage is
used, leave this pin floating.
Internally regulated 1.8-V analog supply voltage. This terminal must
not be used to power external devices.
Internally regulated 1.8V digital supply voltage.This terminal must not
be used to power external devices.
3.3 Regulator output. Not to be used as s supply or connected to any
other components other than decoupling caps. Add decoupling
capacitors with pins 42 and 41.
STEST
SUB_PWM–
SUB_PWM+
TEST1
TEST2
VALID
31
39
40
7
32
36
DI
DO
DO
DI
DI
DO
VR_ANA
VR_DIG
VREG
14
27
43
P
P
P
VREG_EN
18
DI
Pulldown
Voltage regulator enable. Connect directly to GND.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
DVDD, AVDD
PVDD_X
OC_ADJ
Input voltage
OUT_x to PGND_X
BST_x to PGND_X
Input clamp current, I
IK
(V
I
< 0 or V
I
> 1.8 V)
Output clamp current, I
OK
(V
O
< 0 or V
O
> 1.8 V)
Operating free-air temperature
Operating junction temperature range
Storage temperature range, T
stg
(1)
(2)
(3)
3.3-V digital input
5-V tolerant
(2)
(1)
VALUE
Supply voltage
–0.3 to 3.6
–0.3 to 30
–0.3 to 4.2
–0.5 to DVDD + 0.5
–0.5 to DVDD + 2.5
32
(3)
43
(3)
UNIT
V
V
V
V
V
V
V
mA
mA
°C
°C
°C
digital input
±20
±20
0 to 85
0 to 150
–40 to 125
Stresses beyond those listed under
absolute ratings
may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under
recommended operation conditions
are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDA, SCL, and HPSEL.
DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
Copyright © 2008, Texas Instruments Incorporated
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