Logic Diagram (SN74)
30
1
A
B
C
D
E
F
8-INPUT POSITIVE-NAND GATES
2
3
● Y = A•B•C•D•E•F•G•H
● 74AC11xxx: Product Available in Reduced-Noise Advanced
CMOS (11000 Series)
● 74ACT11xxx: Product Available in Reduced-Noise Advanced
CMOS (11000 Series)
4
8
Y
5
6
11
12
G
H
FUNCTION TABLE
INPUTS
A–H
OUTPUT
Y
L
All inputs H
One or more inputs L
H
ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
SN74 CD74 CD74
AC
11
ACT
11
PARAMETER
MAX or MIN
TTL
LS
S
ALS
AS
F
UNIT
HC
HC
HCT
ICC
MAX
MAX
MAX
6
1.1
-0.4
8
10
-1
0.9
-0.4
8
4.9
-2
4
0.02
-4
0.04
-4
0.04
-4
0.04
-24
24
0.04
-24
24
mA
mA
mA
IOH
IOL
-0.4
16
-1
20
20
20
4
4
4
SWITCHING CHARACTERISTICS
SN74 CD74 CD74
AC
11
ACT
11
PARAMETER
INPUT
OUTPUT
MAX or MIN
TTL
LS
S
ALS
AS
F
HC
HC
HCT
tPLH
A thru H
A thru H
Y
Y
MAX
MAX
22
15
15
20
6
7
10
12
5
5.5
5
33
33
39
39
42
42
7.2
7.4
8.5
8.7
tPHL
4.5
UNIT: ns
Logic Diagram
31
DELAY ELEMENTS
(2)
(1)
(3)
A1
A2
Y1
Y2
Y3
(4)
(7)
● Delay Elements for Generating Delay Line
● Inverting and Non-inverting Elements
● Buffer NAND Elements Rated at IOL of 12/24mA
● P-N-P Inputs Reduce Fan-In (IIL = -0.2mA MAX)
● Worst Case MIN/MAX Delays Guaranteed Across
Temperature and VCC Range
(5)
(6)
A3
B3
A4
B4
(10)
(11)
(9)
Y4
Y5
Y6
(12)
(14)
(13)
(15)
A5
A6
ELECTRICAL CHARACTERISTICS AND
RECOMMENDED OPERATING CONDITIONS
SWITCHING CHARACTERISTICS
PARAMETER
MAX or MIN
LS
UNIT
PARAMETER
INPUT
OUTPUT
MAX or MIN
LS
ICC
IOH
MAX
MAX
MAX
MAX
MAX
20
-1.2
-0.4
24
mA
mA
mA
mA
mA
tPLH
65
45
80
95
15
15
A1, A6
A2, A5
Y1, Y6
Y2, Y5
Y3, Y4
MAX
MAX
MAX
Y3, Y4 outputs
tPHL
All other outputs
Y3, Y4 outputs
tPLH
tPHL
IOL
All other outputs
8
tPLH
A3, B3
A4, Y4
tPHL
UNIT: ns
248
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
TI [ TEXAS INSTRUMENTS ]
