SN74LVC2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES203K – APRIL 1999 – REVISED JUNE 2005
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
(1)
CLR
H
L
L
H
H
H
CLK
X
X
X
↑
↑
L
D
X
X
X
H
L
X
Q
H
L
H
(1)
H
L
Q
0
OUTPUTS
Q
L
H
H
(1)
L
H
Q
0
This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
LOGIC DIAGRAM (POSITIVE LOGIC)
PRE
CLK
7
1
C
C
C
5
TG
Q
C
C
C
C
D
2
TG
TG
TG
3
C
CLR
6
C
C
Q
2
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