SN74GTLP21395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001
APPLICATION INFORMATION
operational description
The GTLP21395 is designed specifically for use with the TI 1394 backplane layer controller family to transmit
the 1394 backplane serial bus across parallel backplanes. But, it is a versatile two 1-bit device that also can
provide multiple 1-bit clocks or an ATM read and write clock in multislot parallel backplane applications.
The 1394–1995 is an IEEE designation for a high-performance serial bus. This serial bus defines both a
backplane (e.g., GTLP, VME, FB+, CPCI, etc.) physical layer and a point-to-point cable-connected virtual bus.
The backplane version operates at 25, 50, or 100 Mbps, whereas the cable version supports data rates of 100,
200, and 400 Mbps. Both versions are compatible at the link layer and above. The interface standard defines
the transmission method, media in the cable version, and protocol. The primary application of the cable version
is the interconnection of digital A/V equipment and integration of I/O connectivity at the back panel of personal
computers using a low-cost, scalable, high-speed serial interface. The primary application of the backplane
version is to provide a robust control interface to each daughter card. The 1394 standard also provides new
services such as real-time I/O and live connect/disconnect capability for external devices.
electrical
The 1394 standard is a transaction-based packet technology for cable- or backplane-based environments. Both
chassis and peripheral devices can use this technology. The 1394 serial bus is organized as if it were memory
space interconnected between devices, or as if devices resided in slots on the main backplane. Device
addressing is 64 bits wide, partitioned as 10 bits for bus ID, 6 bits for node ID, and 48 bits for memory addresses.
The result is the capability to address up to 1023 buses, each having up to 63 nodes and each with 281 terabytes
of memory. Memory-based addressing, rather than channel addressing, views resources as registers or
memory that can be accessed with processor-to-memory transactions. Each bus entity is termed a unit, to be
individually addressed, reset, and identified. Multiple nodes can reside physically in a single module, and
multiple ports can reside in a single node.
Some key features of the 1394 topology are multimaster capabilities, live connect/disconnect (hot plugging)
capability, genderless cabling connectors on interconnect cabling, and dynamic node address allocation as
nodes are added to the bus. A maximum of 63 nodes can be connected to one network.
The cable-based physical interface uses dc-level line states for signaling during initialization and arbitration.
Both environments use dominant mode addresses for arbitration. The backplane environment does not have
the initialization requirements of the cable environment because it is a physical bus and does not contain
repeaters. Due to the differences, a backplane-to-cable bridge is required to connect these two environments.
The signals transmitted on both the cable and backplane environments are NRZ with data-strobe (DS)
encoding. DS encoding allows only one of the two signal lines to change each data-bit period, essentially
doubling the jitter tolerance with very little additional circuitry overhead in the hardware.
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