SLLS562G – AUGUST 2009 – REVISED MAY 2009
PARAMETER MEASUREMENT INFORMATION (continued)
V
TEST
100
W
0V
Pulse Generator,
15
m
s Duration,
1% Duty Cycle
15
m
s
15 ms
-V
TEST
Figure 13. Test Circuit and Waveforms, Transient Overvoltage Test
DEVICE INFORMATION
PIN ASSIGNMENT
D, P OR DGK PACKAGE
(TOP VIEW)
R
RE
DE
D
1
2
3
4
8
7
6
5
V
CC
B
A
GND
R
1
D
4
LOGIC DIAGRAM (POSITIVE LOGIC)
3
DE
2
RE
6
7
A
B
FUNCTION TABLE
DRIVER
INPUT
D
H
L
X
Open
X
INPUT
DE
H
H
L
H
Open
OUTPUTS
A
H
L
Z
H
Z
B
L
H
Z
L
Z
RECEIVER
DIFFERENTIAL INPUTS
V
ID
= V
A
- V
B
V
ID
≤
–0.2 V
–0.2 V < V
ID
< –0.01 V
–0.01 V
≤
V
ID
X
Open circuit
Short circuit
IDLE Bus
X
ENABLE
RE
L
L
L
H
L
L
L
Open
OUTPUT
R
L
?
H
Z
H
H
H
Z
Receiver Failsafe
The differential receiver is “failsafe” to invalid bus states caused by:
• open bus conditions such as a disconnected connector,
• shorted bus conditions such as cable damage shorting the twisted-pair together, or
• idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the
receiver is not indeterminate.
Copyright © 2009, Texas Instruments Incorporated
9
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