SLLS562G – AUGUST 2009 – REVISED MAY 2009
PACKAGE THERMAL INFORMATION
PARAMETER
TEST CONDITIONS
Low-k board, no air flow
θ
JA
Junction-to-ambient
thermal resistance
High-k board, no air flow
PACKAGE
MOSP (DGK)
SOIC (D)
PDIP (P)
MOSP (DGK)
SOIC (D)
PDIP (P)
MOSP (DGK)
θ
JB
Junction-to-board
thermal resistance
Low-k board, no air flow
SOIC (D)
PDIP (P)
MOSP (DGK)
θ
JC
Junction-to-case
thermal resistance
Input to D is a 50% duty
cycle square wave at max
rec'd signal rate
R
L
= 54
Ω
V
CC
= 5.5 V, T
J
=
130°C
SOIC (D)
PDIP (P)
ALL HVD3082E
ALL HVD3085E
ALL HVD3088E
ALL
165
Average power
dissipation
Thermal shut-down
junction temperature
MIN
TYP
266
210
155
180
130
70
110
55
40
66
80
80
203
205
276
°C
mW
°C/W
°C/W
°C/W
°C/W
MAX
UNIT
P
(AVG)
T
SD
TYPICAL CHARACTERISTICS
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
80
60
10
SN65HVD3082E
RMS SUPPLY CURRENT
vs
SIGNALING RATE
No Load,
V
CC
= 5 V,
o
T
A
= 25 C
50% Square Wave Input
Driver and Receiver
1
I
I
- Input Bias Current -
m
A
40
20
0
V
CC
= 0 V
V
CC
= 5 V
-20
-40
-60
-8
-6
-4
-2
0
2
4
6
8
10
12
V
I
- Bus Input Voltage - V
I
CC
- Supply Current - mA
Receiver Only
0.1
1
10
Signal Rate - kbps
100
Figure 14.
Figure 15.
Copyright © 2009, Texas Instruments Incorporated
11
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