SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C – APRIL 1982 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
VCC
S1
RL
From Output
Under Test
CL
(see Note A)
RL
Test
Point
R1
From Output
Under Test
CL
(see Note A)
Test
Point
From Output
Under Test
CL
(see Note A)
R2
Test
Point
RL = R1 = R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
Timing
Input
tsu
Data
Input
1.3 V
3.5 V
1.3 V
0.3 V
th
3.5 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
High-Level
Pulse
3.5 V
1.3 V
tw
1.3 V
0.3 V
Low-Level
Pulse
3.5 V
1.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
Control
(low-level
enabling)
tPZL
Waveform 1
S1 Closed
(see Note B)
3.5 V
1.3 V
1.3 V
0.3 V
tPLZ
1.3 V
VOL
0.3 V
VOH
1.3 V
0.3 V
3.5 V
Input
tPLH
In-Phase
Output
1.3 V
1.3 V
1.3 V
0.3 V
tPHL
VOH
1.3 V
VOL
tPLH
VOH
1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V
VOL
[
3.5 V
tPHZ
tPZH
Waveform 2
S1 Open
(see Note B)
tPHL
Out-of-Phase
Output
(see Note C)
[
0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR
≤
1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
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