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SN54ALS74J 参数 Datasheet PDF下载

SN54ALS74J图片预览
型号: SN54ALS74J
PDF下载: 下载PDF文件 查看货源
内容描述: [IC,FLIP-FLOP,DUAL,D TYPE,ALS-TTL,DIP,14PIN,CERAMIC]
分类和应用: 逻辑集成电路触发器
文件页数/大小: 7 页 / 111 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS143C – APRIL 1982 – REVISED AUGUST 1995
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
TYPICAL MAXIMUM
CLOCK FREQUENCY
(CL = 50 pF)
(MHz)
50
134
TYPICAL POWER
DISSIPATION
PER FLIP-FLOP
(mW)
6
26
SN54ALS74A, SN54AS74A . . . J PACKAGE
SN74ALS74A, SN74AS74A . . . D OR N PACKAGE
(TOP VIEW)
TYPE
′ALS74A
′AS74A
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
description
These devices contain two independent
positive-edge-triggered D-type flip-flops. A low
level at the preset (PRE) or clear (CLR) inputs sets
or resets the outputs regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the
setup-time requirements are transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a voltage
level and is not directly related to the rise time of
CLK. Following the hold-time interval, data at the
D input can be changed without affecting the
levels at the outputs.
The SN54ALS74A and SN54AS74A are
characterized for operation over the full military
temperature range of – 55°C to 125°C. The
SN74ALS74A and SN74AS74A are characterized
for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
L
D
X
X
X
H
L
X
SN54ALS74A, SN54AS74A . . . FK PACKAGE
(TOP VIEW)
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
V
CC
2CLR
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
2D
NC
2CLK
NC
2PRE
NC – No internal connection
OUTPUTS
Q
H
L
H†
H
L
Q0
Q
L
H
H†
L
H
Q0
† The output levels in this configuration are not
specified to meet the minimum levels for VOH if the
lows at PRE and CLR are near VIL maximum.
Furthermore, this configuration is nonstable; that
is, it does not persist when PRE or CLR returns to
its inactive (high) level.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1Q
GND
NC
2Q
2Q
1