Features
1
Features
Controlled Baseline
− One Assembly/Test/Fabrication Site
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Clock and System Control
− Dynamic PLL Ratio Changes Supported
− On-Chip Oscillator
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
− Watchdog Timer Module
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Three External Interrupts
Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
Enhanced Product-Change Notification
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Three 32-Bit CPU-Timers
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Qualification Pedigree
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128-Bit Security Key/Lock
− Protects Flash/ROM/OTP and L0/L1
SARAM
High-Performance Static CMOS Technology
− 150 MHz (6.67-ns Cycle Time)
− Low-Power (1.8-V Core @135 MHz, 1.9-V
Core @150 MHz, 3.3-V I/O) Design
− Prevents Firmware Reverse Engineering
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Motor Control Peripherals
− Two Event Managers (EVA, EVB)
− Compatible to 240xA Devices
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JTAG Boundary Scan Support
High-Performance 32-Bit CPU (320C28x)
− 16 x 16 and 32 x 32 MAC Operations
− 16 x 16 Dual MAC
Serial Port Peripherals
− Serial Peripheral Interface (SPI)
− Two Serial Communications Interfaces
(SCIs), Standard UART
− Enhanced Controller Area Network
(eCAN)
− Harvard Bus Architecture
− Atomic Operations
− Fast Interrupt Response and Processing
− Unified Memory Programming Model
− 4M Linear Program/Data Address Reach
− Code-Efficient (in C/C++ and Assembly)
− 320F24x/LF240x Processor Source Code
Compatible
− Multichannel Buffered Serial Port
(McBSP)
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12-Bit ADC, 16 Channels
− 2 x 8 Channel Input Multiplexer
− Two Sample-and-Hold
− Single/Simultaneous Conversions
− Fast Conversion Rate: 80 ns/12.5 MSPS
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On-Chip Memory
− Flash Devices: Up to 128K x 16 Flash
(Four 8K x 16 and Six 16K x 16 Sectors)
− ROM Devices: Up to 128K x 16 ROM
− 1K x 16 OTP ROM
− L0 and L1: 2 Blocks of 4K x 16 Each
Single-Access RAM (SARAM)
− H0: 1 Block of 8K x 16 SARAM
− M0 and M1: 2 Blocks of 1K x 16 Each
SARAM
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Up to 56 General Purpose I/O (GPIO) Pins
Advanced Emulation Features
− Analysis and Breakpoint Functions
− Real-Time Debug via Hardware
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Development Tools Include
− ANSI C/C++ Compiler/Assembler/Linker
− Code Composer Studio IDE
− DSP/BIOS
Low-Power Modes and Power Savings
− IDLE, STANDBY, HALT Modes Supported
− Disable Individual Peripheral Clocks
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Boot ROM (4K x 16)
− With Software Boot Modes
− Standard Math Tables
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External Interface (2812)
− Up to 1M Total Memory
− Programmable Wait States
− Programmable Read/Write Strobe Timing
− Three Individual Chip Selects
Package Options
− 179-Ball MicroStar BGA (GHH), (2812)
− 176-Pin Low-Profile Quad Flatpack
(LQFP) (PGF) (2812)
TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
†
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡
IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port
11
March 2004 − Revised October 2004
SGUS051A
TI [ TEXAS INSTRUMENTS ]
