SPNS174
–
SEPTEMBER 2011
Table 4-31. Interrupt Request Assignments (continued)
Modules
SCI
HET TU2
Ethernet
Ethernet
Ethernet
Ethernet
HWAG1
HWAG2
DCC1
DCC2
Reserved
HWAG1
HWAG2
Reserved
Interrupt Sources
SCI level 1 interrupt
HET TU2 level 1 interrupt
C0_MISC_PULSE
C0_TX_PULSE
C0_THRESH_PULSE
C0_RX_PULSE
HWA_INT_REQ_H
HWA_INT_REQ_H
DCC done interrupt
DCC2 done interrupt
Reserved
HWA_INT_REQ_L
HWA_INT_REQ_L
Reserved
Default VIM Interrupt
Channel
74
75
76
77
78
79
80
81
82
83
84-87
88
89
90-95
NOTE
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR
entry; therefore only request channels 0..94 can be used and are offset by 1 address in the
VIM RAM.
NOTE
The lower-order interrupt channels are higher priority channels than the higher-order interrupt
channels.
NOTE
The application can change the mapping of interrupt sources to the interrupt channels via the
interrupt channel control registers (CHANCTRLx) inside the VIM module.
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2011, Texas Instruments Incorporated
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