SPNS174
–
SEPTEMBER 2011
4.15 Vectored Interrupt Manager
The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the
many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow
of program execution. Normally, these events require a timely response from the central processing unit
(CPU); therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to
an interrupt service routine (ISR).
4.15.1 VIM Features
The VIM module has the following features:
•
Supports 96 interrupt channels.
–
Provides programmable priority and enable for interrupt request lines.
•
Provides a direct hardware dispatch mechanism for fastest IRQ dispatch.
•
Provides two software dispatch mechanisms when the CPU VIC port is not used.
–
Index interrupt
–
Register vectored interrupt
•
Parity protected vector interrupt table against soft errors.
Table 4-31. Interrupt Request Assignments
Modules
ESM
Reserved
RTI
RTI
RTI
RTI
RTI
RTI
RTI
GIO
N2HET1
HET TU1
MIBSPI1
LIN
MIBADC1
MIBADC1
DCAN1
SPI2
Reserved
CRC
ESM
SYSTEM
CPU
GIO
N2HET1
HET TU
MIBSPI
Interrupt Sources
ESM High level interrupt (NMI)
Reserved
RTI compare interrupt 0
RTI compare interrupt 1
RTI compare interrupt 2
RTI compare interrupt 3
RTI overflow interrupt 0
RTI overflow interrupt 1
RTI timebase interrupt
GIO interrupt A
N2HET1 level 0 interrupt
HET TU1 level 0 interrupt
MIBSPI1 level 0 interrupt
LIN level 0 interrupt
MIBADC1 event group interrupt
MIBADC1 sw group 1 interrupt
DCAN1 level 0 interrupt
SPI2 level 0 interrupt
Reserved
CRC Interrupt
ESM Low level interrupt
Software interrupt (SSI)
PMU Interrupt
GIO interrupt B
N2HET1 level 1 interrupt
HET TU level 1 interrupt
MIBSPI level 1 interrupt
Default VIM Interrupt
Channel
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Copyright
©
2011, Texas Instruments Incorporated
System Information and Electrical Specifications
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PRODUCT PREVIEW
4.15.2 Interrupt Request Assignments
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