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RM48L550PGET 参数 Datasheet PDF下载

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型号: RM48L550PGET
PDF下载: 下载PDF文件 查看货源
内容描述: RM48Lx50 16位/ 32位RISC闪存微控制器 [RM48Lx50 16/32-Bit RISC Flash Microcontroller]
分类和应用: 闪存微控制器
文件页数/大小: 157 页 / 2926 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SPNS174
SEPTEMBER 2011
Table 5-9. Dynamic Characteristics for the N2HET Input Capture Functionality
PARAMETER
1
2
3
4
(1)
(2)
Input signal period, PCNT or WCAP for rising edge
to rising edge
Input signal period, PCNT or WCAP for falling edge
to falling edge
Input signal high phase, PCNT or WCAP for rising
edge to falling edge
Input signal low phase, PCNT or WCAP for falling
edge to rising edge
MIN
(1)
(2)
MAX
(1)
(2)
UNIT
ns
ns
ns
ns
2 (hr) (lr) tc
(VCLK2)
+ 2
2 (hr) (lr) tc
(VCLK2)
+ 2
(hr) (lr) tc
(VCLK2)
+ 2
(hr) (lr) tc
(VCLK2)
+ 2
2
25
(hr) (lr) tc
(VCLK2)
- 2
2
25
(hr) (lr) tc
(VCLK2)
- 2
2
25
(hr) (lr) tc
(VCLK2)
- 2
2
25
(hr) (lr) tc
(VCLK2)
- 2
hr = High-resolution prescaler, configured using the HRPFC field of the Prescale Factor Register (HETPFR).
lr = Loop-resolution prescaler, configured using the LFPRC field of the Prescale Factor Register (HETPFR)
Both N2HET1 and N2HET2 have three channels each that are enhanced to be able to capture inputs with
smaller pulse widths than that specified in
These are N2HET1 channels 15, 20 and 31, and
N2HET2 channels 12, 14 and 16.
The input capture capability for these channels is specified in the following table.
Table 5-10. Input Capture Capability for N2HET Channels with Enhancements
PARAMETER
1
2
3
4
Input signal period, PCNT or WCAP for rising edge
to rising edge
Input signal period, PCNT or WCAP for falling edge
to falling edge
Input signal high phase, PCNT or WCAP for rising
edge to falling edge
Input signal low phase, PCNT or WCAP for falling
edge to rising edge
MIN
(hr) (lr) tc
(VCLK2)
+ 2
(hr) (lr) tc
(VCLK2)
+ 2
2 (hr) tc
(VCLK2)
+ 2
2 (hr) tc
(VCLK2)
+ 2
2
25
MAX
(hr) (lr) tc
(VCLK2)
- 2
UNIT
ns
ns
ns
ns
PRODUCT PREVIEW
2
25
(hr) (lr) tc
(VCLK2)
- 2
2
25
(hr) (lr) tc
(VCLK2)
- 2
2
25
(hr) (lr) tc
(VCLK2)
- 2
5.4.4
N2HET1-N2HET2 Interconnections
In some applications the N2HET resolutions must be synchronized. Some other applications require a
single time base to be used for all PWM outputs and input timing captures.
The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures
the N2HET in master or slave mode (default is slave mode). A N2HET in master mode provides a signal
to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to
the loop resolution signal sent by the master. The slave does not require this signal after it receives the
first synchronization signal. However, anytime the slave receives the re-synchronization signal from the
master, the slave must synchronize itself again..
NHET1
EXT_LOOP_SYNC
NHET_LOOP_SYNC
NHET2
NHET_LOOP_SYNC
EXT_LOOP_SYNC
Figure 5-6. N2HET1
N2HET2 Synchronization Hookup
5.4.5
5.4.5.1
N2HET Checking
Internal Monitoring
To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be
used to monitor each other’s signals as shown in
The direction of the monitoring is controlled
by the I/O multiplexing control module.
128
Peripheral Information and Electrical Specifications
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2011, Texas Instruments Incorporated