SPNS174
–
SEPTEMBER 2011
Table 4-28. EMIF Asynchronous Memory Switching Characteristics
(continued)
NO
Parameter
MIN
Output hold time, EMIFnWE
high to EMIFCS[4:2] high (SS =
1)
18
19
20
21
22
t
su(EMDQMV-EMWEL)
t
h(EMWEH-EMDQMIV)
t
su(EMBAV-EMWEL)
t
h(EMWEH-EMBAIV)
t
su(EMAV-EMWEL)
Output setup time, EMIFBA[1:0]
valid to EMIFnWE low
Output hold time, EMIFnWE
high to EMIFBA[1:0] invalid
Output setup time, EMIFBA[1:0]
valid to EMIFnWE low
Output hold time, EMIFnWE
high to EMIFBA[1:0] invalid
Output setup time,
EMIFADDR[21:0] valid to
EMIFnWE low
Output hold time, EMIFnWE
high to EMIFADDR[21:0] invalid
EMIFnWE active low width (EW
= 0)
EMIFnWE active low width (EW
= 1)
25
26
t
d(EMWAITH-EMWEH)
t
su(EMDV-EMWEL)
Delay time from EMIFnWAIT
deasserted to EMIFnWE high
Output setup time,
EMIFDATA[15:0] valid to
EMIFnWE low
Output hold time, EMIFnWE
high to EMIFDATA[15:0] invalid
-3
Value
NOM
0
MAX
+3
ns
Unit
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
(WS)*E+3
ns
ns
ns
ns
ns
23
24
t
h(EMWEH-EMAIV)
t
w(EMWEL)
(WH)*E-3
(WST)*E-3
(WST+(EWC*1
6)) *E-3
3E-3
(WS)*E-3
(WH)*E
(WST)*E
(WST+(EWC*1
6))*E
4E
(WS)*E
(WH)*E+3
(WST)*E+3
(WST+(EWC*1
6)) *E+3
4E+3
(WS)*E+3
ns
ns
ns
ns
ns
27
t
h(EMWEH-EMDIV)
(WH)*E-3
(WH)*E
(WH)*E+3
ns
Table 4-29. EMIF Synchronous Memory Timing Requirements
NO.
19
Parameter
t
su(EMIFDV-EM_CLKH)
Input setup time, read data valid on
EMIFDATA[15:0] before EMIF_CLK
rising
Input hold time, read data valid on
EMIFDATA[15:0] after EMIF_CLK
rising
MIN
1
MAX
Unit
ns
20
t
h(CLKH-DIV)
1.5
ns
Table 4-30. EMIF Synchronous Memory Switching Characteristics
NO.
1
2
3
4
5
6
7
Parameter
t
c(CLK)
t
w(CLK)
t
d(CLKH-CSV)
t
oh(CLKH-CSIV)
t
d(CLKH-DQMV)
t
oh(CLKH-DQMIV)
t
d(CLKH-AV)
Cycle time, EMIF clock EMIF_CLK
Pulse width, EMIF clock EMIF_CLK
high or low
Delay time, EMIF_CLK rising to
EMIFnCS[0] valid
Output hold time, EMIF_CLK rising to
EMIFnCS[0] invalid
Delay time, EMIF_CLK rising to
EMIFnDQM[1:0] valid
Output hold time, EMIF_CLK rising to
EMIFnDQM[1:0] invalid
Delay time, EMIF_CLK rising to
EMIFADDR[21:0] and EMIFBA[1:0]
valid
1
7
1
7
MIN
15
5
7
MAX
Unit
ns
ns
ns
ns
ns
ns
ns
Copyright
©
2011, Texas Instruments Incorporated
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