SPNS174
–
SEPTEMBER 2011
NOTE
•
A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
The maximum t
h(SDA-SCLL)
has only to be met if the device does not stretch the LOW
period (t
w(SCLL)
) of the SCL signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the
requirement t
su(SDA-SCLH)
≥
250 ns must then be met. This will automatically be the case if
the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr max + t
su(SDA-SCLH)
.
C
b
= total capacitance of one bus line in pF. If mixed with fast-mode devices, faster
fall-times are allowed.
•
•
•
PRODUCT PREVIEW
136
Peripheral Information and Electrical Specifications
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