SPNS174
–
SEPTEMBER 2011
5.8.2
I2C I/O Timing Specifications
Table 5-14. I2C Signals (SDA and SCL) Switching Characteristics
(1)
Parameter
Standard Mode
MIN
MAX
149
75.2
10
4.7
4
4.7
4
250
0
4.7
4.0
3.45
(2)
Fast Mode
MIN
75.2
2.5
0.6
0.6
1.3
0.6
100
0
1.3
0.6
0
400
50
400
0.9
MAX
149
ns
ms
ms
ms
ms
ms
ns
ms
ms
ms
ns
pF
Unit
t
c(I2CCLK)
t
c(SCL)
t
su(SCLH-SDAL)
t
h(SCLL-SDAL)
t
w(SCLL)
t
w(SCLH)
t
su(SDA-SCLH)
t
h(SDA-SCLL)
t
w(SDAH)
t
su(SCLH-SDAH)
t
w(SP)
C
b
(1)
(2)
(3)
(3)
Cycle time, Internal Module clock for I2C,
prescaled from VCLK
Cycle time, SCL
Setup time, SCL high before SDA low (for a
repeated START condition)
Hold time, SCL low after SDA low (for a repeated
START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low (for I2C bus
devices)
Pulse duration, SDA high between STOP and
START conditions
Setup time, SCL high before SDA high (for STOP
condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
The maximum t
h(SDA-SCLL)
for I2C bus devices has only to be met if the device does not stretch the low period (t
w(SCLL)
) of the SCL
signal.
C
b
= The total capacitance of one bus line in pF.
SDA
t
w(SDAH)
t
w(SCLL)
t
r(SCL)
SCL
t
c(SCL)
t
h(SDA-SCLL)
t
h(SCLL-SDAL)
Stop
Start
Repeated Start
t
f(SCL)
t
h(SCLL-SDAL)
t
su(SCLH-SDAL)
t
w(SCLH)
t
su(SDA-SCLH)
t
w(SP)
t
su(SCLH-SDAH)
Stop
Figure 5-8. I2C Timings
Copyright
©
2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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