ADS1259
www.ti.com
SBAS424C –JUNE 2009–REVISED MARCH 2010
NOISE PERFORMANCE
MODULATOR
The ADS1259 offers excellent noise performance that
can be optimized by adjusting the data rate and by
selection of the digital filter mode. As the averaging is
increased by reducing the data rate, the noise drops
correspondingly. Additionally, because the sinc2
digital filter provides more filtering than the sinc1
digital filter, sinc2 provides lower noise conversions.
Table 1 shows the noise as a function of data rate
and filter mode.
The
high-performance
modulator
is
an
inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined
structure, as shown in Figure 32. It shifts the
quantization noise to a higher frequency (out of the
passband) where digital filtering can easily remove it.
fMOD = fCLK/8
2nd-Order
DS
Analog Input (VIN
)
1st-Stage
Table 1 expresses typical noise data in several ways:
RMS noise, effective number of bits (ENOB), and
noise-free bits. ENOB is calculated from Equation 1:
To Digital Filter
2nd-Order
DS
2nd-Stage
FSR
ln
4th-Order Modulator
RMS Noise
ENOB =
ln(2)
Figure 32. Fourth-Order Modulator
Where:
FSR = 2VREF
(1)
The modulator first stage converts the analog input
voltage into a pulse-code modulated (PCM) stream.
When the level of differential analog input (AINP –
AINN) is near the level of the reference voltage
(VREFP – VREFN), the 1s density of the PCM data
stream is at its highest. When the level of the
differential analog input is near zero, the PCM 0s and
1s densities are nearly equal. At the two extremes of
the analog input levels (+FS and –FS), the 1s density
of the PCM streams are approximately +90% and
+10%, respectively.
The calculation of noise-free bits uses the same
formula as Equation 1, except that the peak-to-peak
noise value is used instead of RMS noise.
ADC
The analog-to-digital converter (ADC) section of the
ADS1259 is composed of two blocks: a high accuracy
modulator and a programmable digital filter.
The modulator second stage produces a 1s density
data stream designed to cancel the quantization
noise of the first stage. The data streams of the two
stages are then combined in the digital filter stage.
Table 1. Typical Noise Data vs Data Rate and Digital Filter(1)
SINC1 DIGITAL FILTER
SINC2 DIGITAL FILTER
DATA
RATE
(SPS)
SAMPLE
SIZE(2)
NOISE
NOISE
ENOB
(RMS)
NOISE-
FREE BITS
NOISE
NOISE
ENOB
(RMS)
NOISE-
FREE BITS
(mVRMS
)
(mVPP
1.8
2.4
3.5
4
)
(mVRMS
0.45
0.5
)
(mVPP
1.6
2
)
10
16.6
50
128
256
0.5
23.3
23.1
22.9
22.8
21.8
21.1
20.3
19.6
21.4
21.0
20.4
20.3
19.0
18.2
17.3
16.6
23.4
23.3
23.0
22.9
22.0
21.3
21.6
21.3
20.7
20.4
19.2
18.4
0.55
0.65
0.7
512
0.6
3
60
512
0.65
1.2
3.5
8.3
14
400
4096
8192
8192
8192
1.4
9.5
17
1200
3600
14400
2.3
2
3.9
32
3.4
(3)
27
(3)
20.5
(3)
17.5
(3)
6.2
50
(1) Noise data taken with shorted analog inputs and internal 2.5V reference using the circuit of Figure 63.
(2) Data sample sizes used for analysis.
(3) Same as sinc1 mode.
Copyright © 2009–2010, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): ADS1259
TI [ TEXAS INSTRUMENTS ]
